Title: High-Performance JIT-Compiled Frameworks for Mobile Devices: Hardware/Compiler Co-Optimization
University of Illinois at Urbana-Champaign
Time: March 27th 10:00am
Location: EB 3105
I also show how the compiler can use Hardware Transactional Memory (HTM) support to perform alias speculation. The approach consists of performing optimizations assuming the alias relationships that are true most of the time, and using the hardware to detect when such relationships are found not to hold through runtime checks. If the assumptions are correct, the code experiences good speedups; otherwise, the transaction is aborted.
The compiler can also use the same HTM support to enforce high-performance Sequential Consistency (SC) for programmability and security. The idea is to wrap large sections of code inside a transaction, and then optimize the code inside each transaction without concern for consistency-model restrictions. The optimizations speculate that any violation of the memory model will not be seen by other threads; otherwise, the transaction is aborted.
Overall, these three approaches allow JIT compilers to achieve high performance in mobile systems, while still maintaining programmability and security.
Wonsun Ahn is a Postdoctoral Research Scientist at the University of Illinois at Urbana-Champaign. His research interests are parallel computer architecture and compilation systems. He is currently the co-PI of an NSF grant on improving the performance of scripting languages. He received a PhD in Computer Science from the same university in 2012. His PhD work was recognized by an IEEE Micro's Top Picks award publication. He has (co-)authored 12 journal and conference papers that have appeared in top compiler and architecture venues, and has two industry patents. He has served in the program and organizational committees of conferences, and is a member of the Samsung Frontier Membership.